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Generate clock signal for MAX297
2020 年 02 月 11 日
16:29:59
ray_1
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Forum Posts: 3
Member Since:
2017 年 10 月 15 日
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I'm trying to set up a ADC / DAC chain using the 86Duino One's built-in ADC/PWM pins to acquire and process audio signals.
To keep the fidelity fairly high, I'm going to use 2x MAX297 ICs as programmable anti-aliasing / reconstruction low-pass filters.

The MAX297 is a high performance switched capacitor 8th order elliptic lowpass and can be programmed by means of an external clock source, that is 50 times the cut-off frequency. This would allow for configuring the sample-rate via software in order to balance audio bandwidth vs. CPU.

Let me give an example: Using the TimerOne lib I can set up a sampling rate of ~31kHz giving a Nyquist rate of ~15kHz. The TimerOne ISR would aqcuire, process and write my audio samples. The MAX297 has a transition bandwidth of r=1.5 so, setting its cut-off frequency to fc=10kHz (fstop=15kHz) requires a clock source of 0.5 MHz.

How would I go about setting up two timer ISRs, one at 1Mhz that toggles an arbitrary digital pin to generate the 0.5 Mhz clock signal, another one running at audio sample rate that's acquiring, processing and writing the audio samples?

TimerOne only gives me the option of running one timer at a fixed rate.

Thanks in advance!

Best,
Ray

2020 年 02 月 13 日
16:43:14
ray_1
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Forum Posts: 3
Member Since:
2017 年 10 月 15 日
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Ok, let me try to put it differently:

Is it possible to run different PWM pins at different periods and have only one of them trigger an ISR? Please see the timing diagram below.

What I need is:

1. One or two pins running at 32us PWM period to output my audio signal. This slower timer should trigger the ISR
2. One free running pin that generates the clock signal at 2us PWM period at a fixed 50% duty cycle, no ISR is needed here in order not to hog the CPU.

http://s390174849.online.de/86timing.png

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